Added CSRs

User status register (ustatus)

UXLEN-1 5   4    3  1    0
│  WPRI  │ UPIE │ WPRI │ UIE │
  UXLEN-5   1       3     1

ustatus is a UXLEN bit-long read/write register that records and controls the current operating status of the hardware thread.

User-state interrupts are disabled when the user-state interrupt enable bit UIE is zero. In order to provide atomicity to the user-state fall-in handler, the value in UIE is copied to UPIE when a user-state interrupt occurs, and UIE is set to zero.

The UIE and UPIE are mirrors of the corresponding bits in mstatus and sstatus.

The privilege level before entering the user state interrupt handler function can only be the user state, so the UPP bit is not required.

The instruction URET is used to return from a user-state trapped state. uRET copies UPIE back to UIE, then sets UPIE in place, and finally copies uepc to pc.

Setting UPIE after UPIE/UIE stack pop is to enable interrupts, and to help find errors in the code.

User is caught in vector base address register (utvec)

| BASE[UXLEN-1 : 2] | MODE |

utvec is a UXLEN bit-long read/write register that stores the settings of the vector into which the vector falls, including the vector base address (BASE) and the vector mode.

The BASE in utvec is a WARL field that can store any valid virtual or physical address, and the address needs to be aligned to 4 bytes. Other vector modes may have additional alignment constraints.

value name description
0 direct base
1 vectored base + 4 * cause

User interrupt registers ( uip and uie )

uip and uie are both UXLEN bit read/write registers, where uip stores the pending interrupt information and uie stores the corresponding interrupt enable bit.

UXLEN-1  9    8   7    5    4   3    1    0

  UXLEN-9     1      3      1      3      1

Three types of interrupts are defined: software interrupts, clock interrupts, and external interrupts. User-state software interrupts are triggered by setting the software interrupt wait bit (USIP) of uip of the current hardware thread. Clearing this bit clears the pending software interrupt. When the USIE in uie is zero, user-state software interrupts are disabled.

The ABI should provide a mechanism for sending cross-core interrupts to other hardware threads, which will eventually set the USIP bit in the uip register of the receiving hardware thread.

Except for USIP, the other bits in uip are read-only in the user state.

If the UTIP bit in the uip register is set, a pending user state clock interrupt will be generated. When the UTIE bit in the uie register is set to zero, the user state clock interrupt is disabled. the ABI should provide a mechanism to clear the pending clock interrupt.

If the UEIP bit in the uip register is set, a pending user state external interrupt will be generated. When the UEIE bit in the uie register is set, the user-state external interrupt is disabled. the ABI should provide mechanisms to mask, unmask, and query the cause of the external interrupt.

The uip and uie registers are a subset of the mip and mie registers. A read or write operation to any field of uip / uie is equivalent to a read or write to the corresponding field of mip / mie. If the system implements S mode, the uip and uie registers are also subsets of the sip and sie registers.

Kernel-state trap delegation registers ( sedeleg and sideleg)

To improve the performance of interrupt and exception handling, separate read/write registers sedeleg and sideleg can be implemented, where the bits are set to delegate specific interrupts and exceptions to the user-state fall-in handler. These two registers have the same layout as the corresponding machine-state caught delegate registers ( medeleg and mideleg). Only the bits corresponding to a trap that has been delegated to the S state are writable, the rest of the bits are held to 0 by the hardware, i.e. only traps delegated to the S state may be delegated to the U state.

When a trap is delegated to a mode u with lower privileges, the ucause register is written with the cause of the trap; the uepc register is written with the virtual address of the instruction in which the trap occurred; the utval register is written with a specific exception data; the UPIE field of mstatus is written with the value of the UIE field at the time of the trap; the mstatus The UIE field of mstatus is cleared to zero. The mcause / scause and mepc / sepc registers and the MPP and MPIE fields of mstatus are not written.

An implementation should not rigidly specify that any delegate bit is one, i.e., any trap that can be delegated must support not being delegated. One implementation option is to select a subset of delegatable traps. The supported delegatable bits can be determined by writing 1 to each bit position and then reading back the value in medeleg / sedeleg or mideleg / sideleg to see which bits have 1 on them.

Currently, triggering a low privilege level fall-in is not supported

will not occur in the user state should hardware constant zero, such as ECall from S/H/M-mode


The uscratch register is a UXLEN bit read/write register.

user exception program counter ( uepc )

uepc is a UXLEN bit read/write register. The lowest bit (uepc[0]) is constant for sub-uepc` depending on the alignment requirements of the implementation.

uepc is a WARL register that must be able to store all valid virtual addresses, but does not need to be able to store all possible invalid addresses. Implementations may convert some illegal addresses to other illegal addresses before writing them to uepc.

When trapped in user state processing, the virtual address of the instruction that was interrupted or triggered the exception is written to uepc, except that uepc is never written by the hardware implementation, but may be written explicitly by software.

User trapped cause register ( ucause )

| Interrupt | Exception Code (WLRL) |

ucause is a UXLEN bit-length read/write register. The event number that triggered the fall is written to ucause when the fall is processed in user state, except that ucause is never written by hardware implementation, but may be written explicitly by software.

Interrupt Exception Code Description
1 0 User State Software Interrupt
1 1-3 Reserve
1 4 User-state clock interrupts
1 5-7 reserved
1 8 User-state external interrupts
1 9-15 reserved
1 ≥16 used by platform
0 0 Instruction address unaligned
0 1 Instruction access error
0 2 illegal instructions
0 3 Breakpoint
0 4 Load address not aligned
0 5 Load access error
0 6 Store/atomic memory operation address not aligned
0 7 Memory/atomic memory operation access error
0 8 User state environment call
0 9-11 Reservation
0 12 Instruction page error
0 13 Load page error
0 14 Reserved
0 15 Storage/atomic memory operation page errors
0 16-23 Reserved
0 24-31 Custom Usage
0 32-47 Reserved
0 48-63 Custom Usage
0 ≥64 reserved

User fall-in-value register ( utval )

utval is a UXLEN bit read/write register. When a trap is handled in the user state, information related to a specific exception is written to utval to help the software handle the trap, except that utval is never written by the hardware implementation, but may be written explicitly by the software. The hardware platform specifies which exceptions must write information to utval and which exceptions will be written unconditionally to 0.

When a hardware breakpoint is triggered, or an instruction/load/store address misalignment/access error/page error exception is thrown, it causes the wrong virtual address to be written to utval. When an illegal instruction exception is thrown, the first XLEN or ILEN bits of the corresponding instruction may be written to utval. For other exceptions, utval is set to 0, but future standards may redefine the setting of utval.

N Extended instructions


uret sets pc to uepc and ustatus.UIE to ustatus.UPIE, thus restoring the state before the interrupt.